A New Hardware Algorithm for Fast IP Routing Targeting Programmable Routers

While deployment of embedded and distributed network services imposes new demands for flexibility and programmability, IP address lookup has become significant performance bottleneck for the highest performance routers. Amid their vast array of academic and commercial solutions to the problem, few achieve a favorable balance of performance, efficiency, and cost. New commercial products utilize Content Addressable Memory (CAM) devices that achieve high lookup speeds and an exorbitantly high hardware cost with limited flexibility. In this paper a new IP forwarding hardware algorithm, based on gray-code encoding, along with its dedicated scalable lookup engine is proposed. The corresponding programmable router is able to achieve high performance with the use of a small portion of Dynamic Reconfigurable Logic (DRL) device and a commodity Random Access Memory (RAM) logic. Experimental evaluation using Ns2 simulator and a small routing table from Mae West [1] has been conducted. The results show that the programmable router can be scaled to achieve guaranteed worst-case performance of over 66 million lookups per second with a single SRAM operation at the fairly clock of 100 MHz. Key-Words: IP forwarding, Internet Router, FPGA, DRL, Networking, distributed hardware.